1. Field of the Invention
The present invention relates to a charge pumping circuit and a clock generator.
2. Description of the Related Art
A recent information recording apparatus for data write/readout to/from a recording medium such as an optical disk (e.g., CD-R or DVD-R/RW) obtains the rotation sync signal of the recording medium and extracts a synchronous clock based on it. The information recording apparatus uses the clock as a recording clock in data recording processing. A PLL (Phase Locked Loop) circuit is generally used to extract such periodic clock. When write-accessing a recording medium, a DLL (Delay Locked Loop) circuit is used to control the pulse timing position of a recording pulse based on a predetermined recording strategy of the recording medium. The PLL circuit or DLL circuit commonly uses a charge pumping circuit.
A general charge pumping circuit charges or discharges a charging pump capacitance. The charging is controlled based on a charging current value and the length of on-state time while a charging control switch for controlling the charging time of the charging pump capacitance is on. The discharging is controlled based on a discharging current value and the length of on-state time while a discharging control switch for controlling the discharging time of the charging pump capacitance is on. A PLL circuit controls the length of the on-state time of the charging control switch and the length of the on-state time of the discharging control switch, based on the phase difference and/or the frequency difference between an externally supplied external clock and a clock based on an internal clock output from a voltage controlling generation circuit. A DLL circuit controls them based on the phase difference between an external clock and a desired tap clock. When the charging amount to the charging pump capacitance is equivalent to the discharging amount from the charging pump capacitance, a control voltage that is generated by the charging pump capacitance and that is supplied to the voltage controlling generation circuit become stabilized.
When the charging current value is equivalent to the discharging current value, the length of on-state time during while the charging control switch for controlling the charging time of the charging pump capacitance is on become equivalent to the length of on-state time while the discharging control switch for controlling the discharging time of the charging pump capacitance is on. This allows precise control of the operation timing of the PLL circuit or DLL circuit.
However, if the charging current value and the discharging current value have a difference, and an operation is performed to equalize the charging amount and the discharging amount, a time lag corresponding to the current difference is generated between the length of on-state time while the charging control switch is on and the length of on-state time while the discharging control switch is on. This time lag results in a shift from the ideal operation timing of the PLL circuit or DLL circuit. The time lag in the charge pumping circuit causes instability in the synchronous clock based on the rotation sync signal of a recording medium such as an optical disk. Additionally, the mark length or edge position of a recording mark recorded on the recording medium goes outside the adequate range. This degrades information reproduction quality causing such effects as a jitter characteristic upon reproduction.
FIG. 1 of Japanese Patent Laid-Open No. 2000-224034 illustrates a charge pump 10 which decreases a control voltage to a VCO by outputting a current to an active filter 17 or increases the control voltage to the VCO by sinking a current from the active filter 17. In the charge pump 10, an operational amplifier OP1 acts to equalize a voltage V2 of the common node between a switch S1 and a switch S2 and a voltage V1 of the noninverting input terminal of the operational amplifier OP1. In the charge pump 10, a feedback loop which passes through transistors Q6 and Q4 acts to equalize a voltage V3 of the noninverting input terminal of an operational amplifier OP2 and the voltage V1 of the noninverting input terminal of the operational amplifier OP2. This control achieves V3=V2=V1 so that the voltage V1 of a bias power supply 171 fixes the collector voltages of transistors Q2 and Q4. At this time, since the input impedance of the operational amplifier OP2 is high, a current i4 flowing to the transistor Q4 is nearly equal to a current i2 flowing to the transistor Q2.
Japanese Patent Laid-Open No. 2000-224034 describes that, when W1 denotes the area ratio of the transistors Q4 and Q5, a current i5 flowing to the transistor Q5 is W1 times the current i4 flowing to the transistor Q4. Japanese Patent Laid-Open No. 2000-224034 also describes that, when W1 denotes the area ratio of the transistors Q2 and Q3, a current i3 flowing to the transistor Q3 is W1 times the current i2 flowing to the transistor Q2. That is, according to Japanese Patent Laid-Open No. 2000-224034, since a relation “i3=i2×W1=i4×W1=i5” is achieved, it therefore should be possible to guarantee i3=i5, that is, equalize the value of the output current and that of the sink current in association with the voltage V1.
However, the area ratio of the transistors Q4 and Q5 may differ greatly from that of the transistors Q2 and Q3 because of variations in the manufacturing process of the transistors Q2 to Q5. In this case, since the ratio of i3 to i2 is greatly different from the ratio of i5 to i4 (the above-described relation is not achieved), it is difficult to guarantee that the output and sink currents having the same value.
FIG. 3 of Japanese Patent Laid-Open No. 2006-270225 illustrates a charge pumping circuit 6 which outputs, from an output node N11, a charging current to charge a capacitance C1 of an LPF 8 or flows, from the output node N11 to the Vss side, a discharging current to discharge the capacitance C1 of the LPF 8. A correction charging pump current ΔIpch to equalize the charging current and the discharging current flows to the charge pumping circuit 6 in accordance with a comparison amplification signal supplied from a charge pumping correction circuit 9.
Japanese Patent Laid-Open No. 2006-270225 describes that the charge pumping correction circuit 9 includes a Pch MOS transistor PT1a whose gate has a gate size (gate length or gate width) K times that of a Pch MOS transistor PT1 for generating the charging current. A bias circuit 7 supplies the same bias voltage Vp to the gate of the Pch MOS transistor PT1 and that of the Pch MOS transistor PT1a. This prior art document also describes that the charge pumping correction circuit 9 includes an Nch MOS transistor NT2a whose gate has a gate size (gate length or gate width) K times that of an Nch MOS transistor NT2 for generating the discharging current. The bias circuit 7 supplies the same bias voltage Vn to the gate of the Nch MOS transistor NT2 and that of the Nch MOS transistor NT2a. The charge pumping correction circuit 9 generates the comparison amplification signal and supplies it to the charge pumping circuit 6 to equalize a first current flowing to the Pch MOS transistor PT1a and a second current flowing to the Nch MOS transistor NT2a. According to Japanese Patent Laid-Open No. 2006-270225, this can equalize the charging current and the discharging current.
However, the gate size ratio of the MOS transistors PT1 and PT1a may differ greatly from that of the MOS transistors NT2 and NT2a because of variations in the manufacturing process of the MOS transistors PT1, PT1a, NT2, and NT2a. In this case, since the ratio of the charging current to the first current is greatly different from the ratio of the discharging current to the second current, it is difficult to equalize the charging current and the discharging current.